ニュース

Microsemi adds to RISC-V based FPGAs

The architecture, developed in collaboration with RISC-V champions SiFive, has a 2Mbyte L2 memory that can be configured as a cache, scratchpad or a direct access memory. “This allows designers to implement deterministic real-time embedded applications simultaneously with an operating system for applications in collaborative, networked IoT systems,” said the firm.

Debug capabilities include instruction trace, 50 breakpoints, passive run-time configurable AXI (Advanced eXtensible Interface) bus monitors and FPGA fabric monitors, as well as a two-channel logic analyser (branded SmartDebug).

Reliability and security features include single error correction and double error detection (SEC-DED) on all memories, physical memory protection, a differential power analysis (DPA) safe crypto core, secure boot and 128kbit flash boot memory.

“In an era of computing driven by the convergence of 5G, machine learning and IoT, embedded developers need the richness of Linux-based operating systems,” said Microchip. “These must meet deterministic system requirements in ever lower power, thermally-constrained design environments, while addressing critical security and reliability requirements.”

Support comes from the Antmicro Renode system modelling platform, which is now integrated with Microchip’s SoftConsole IDE. A development kit is also available, consisting of the PolarFire FPGA-enabled ‘HiFive unleashed’ expansion board and SiFive’s HiFive unleashed development board with its RISC-V microprocessor subsystem.

As part of today’s announcement, Microchip is launching a ‘Mi-V embedded experts program’ – a worldwide partner network to assist customers in hardware/software designs for PolarFire. “This programme ensures support throughout the lifecycle of customer products and helps to jump-start designs. Members also get access to direct technical support and early access to development platforms and silicon,” said Microchip.